1. Field of the Invention
The present invention relates to a method of forming a local interconnect. More particularly, the present invention relates to a method of forming a local interconnect using a dual damascene process with self-aligning properties.
2. Description of Related Art
In many highly integrated semiconductor products, designs having two or more metallic interconnect layers, know also as multi-level interconnects, are often used. The reason for having a three-dimensional wiring line structure is for accommodating the increased interconnection due to an increase in device density. In general, multi-level interconnects are formed by first providing a first layer or a lower layer of metallic wiring and interconnect structure. Then, a second layer of metallic wiring for connecting with the first layer of metallic wiring and interconnect structure is formed. The first layer of metallic wiring is usually a polysilicon layer or a metallic layer, and the first layer of metallic wiring is electrically connected to one of the source/drain regions of a substrate. In order to connect to more devices, a second layer or more layers of the metallic wiring are used.
When dimensions of the devices are reduced to the deep-submicron range, a number of defects emerge when using the aforementioned method. For example, if the conductive material for forming the plug is copper, there are be some difficulties in providing an appropriate etchant for etching back the copper layer. In addition, difficulties in fabricating the wiring line structures increase, especially when metal is being deposited into a via plug or when dielectric material is being deposited into the recess cavities between metallic wiring.
Due to poor step coverage of the metal, voids may be generated between the metallic wires and some impurities may be trapped in between these areas. Consequently, an alternative method called a dual damascene method is more frequently used. The dual damascene method of forming interconnects is able to avoid most of the defects that are due to a reduction in device dimensions. Moreover, a planarized dielectric layer surface is eventually obtained.
Normally, the via plug of a multi-level metallic interconnect is formed by first forming an insulating layer over a metallic layer, and then forming a patterned photoresist layer over the insulating layer. Thereafter, etching is carried out to form a via hole, and then conductive material is deposited into the via hole. In general, the conductive material for forming the via plug is tungsten. Finally, metallic interconnects for connecting devices are formed over the insulating layer, thereby completing the process of fabricating a multi-level metallic interconnect. The process of fabricating a multi-level metallic interconnect is explained further with reference to FIGS. 1A through 1H.
FIGS. 1A through 1H are cross-sectional views showing the progression of manufacturing steps in producing interconnects according to a conventional method.
First, as shown in FIG. 1A, a substrate structure 100 (to simplify the figure, devices within the substrate structure 100 are not drawn) having a planarized surface is provided. Then, a metallic layer 101 is formed over the substrate structure 100. Thereafter, a patterned photoresist layer 104 is formed over the metallic layer 101 so that areas for forming metallic wires are covered.
Next, as shown in FIG. 1B, the metallic layer 101 is etched using the photoresist layer 104 as a mask. Hence, metallic lines 101a and 101b are formed above the substrate structure 100 while the substrate surface is exposed. Thereafter, the photoresist layer 104 is removed.
In the subsequent step, as shown in FIG. 1C, an insulating layer 105, for example, a silicon oxide layer is deposited over the substrate structure 100. Then, excess insulating layer 105 above the metallic lines 101a and 101b is removed using, for example, a chemical-mechanical polishing (CMP) method. Ultimately, the top surfaces of the metallic lines 101a and 101b are exposed.
Next, as shown in FIG. 1D, another insulating layer 106 a silicon oxide layer, for example, is deposited over the substrate structure 100, covering the metallic lines 101a, 101b and the insulating layer 105. The thickness of the insulating layer 106 depends on the height of the vertical plug required. Thereafter, the insulating layer 106 is planarized, and then another patterned photoresist layer 114 that exposes the area for forming a via hole is formed over the insulating layer 106. The via hole should correspond in position to the conductive line 101a.
Next, as shown in FIG. 1E, the insulating layer 106 is etched using the photoresist layer 114 as a mask. Hence, a via hole 107 that exposes the conductive line 101a is formed within the insulating layer 106a. Thereafter, the photoresist layer 114 is removed. As the line width of semiconductor devices continue to be reduced, misalignment problems intensify when the via hole 107 is formed above the conductive line 101a using the conventional process.
Next, as shown in FIG. 1F, a glue/barrier layer 112 conformal to the via hole surface is deposited over the substrate structure 100. The glue/barrier layer 112 mainly serves to increase the adhesion between a subsequently deposited metallic layer and other materials. Thereafter, the metallic layer is deposited over the substrate structure 100. For example, a layer of tungsten is deposited over the substrate and fills the via hole 107 using, for example, a chemical vapor deposition method. Consequently, a tungsten plug that couples electrically with the conductive line 101a is formed. After that, an etching back operation is carried out to remove excess metal on the surface of the insulating layer 106a, thereby forming a metal plug 110. However, in the above conventional process of depositing metal into the via hole, problems caused by poor step coverage of the metal often occur.
Next, as shown in FIG. 1G, yet another metallic layer 111 is deposited over the substrate structure 100, and then the metallic layer 111 is planarized. A patterned photoresist layer 124 is again formed on the surface of the metallic layer 111, covering areas for forming other interconnecting lines.
Next, as shown in FIG. 1H, the metallic layer 111 is etched using the photoresist layer 124 as a mask. Finally, the photoresist layer 124 is removed to form a conductive line 111a above the substrate structure 100, wherein the conductive line 111a couples electrically with the metal plug 110.
At present, another method known as a dual damascene process is often used in the fabrication of interconnects. The dual damascene technique provides a more stable and reliable method of fabricating integrated circuits. The technique makes used of a chemical-mechanical polishing (CMP) operation to form the required metallic line pattern, unlike the conventional method that requires an etching back operation. Hence, a host of metals including, for example, aluminum, copper and aluminum alloy can be selected. With this many metals to choose from, metallic interconnects having suitable resistance level and electromigration property can be found. Therefore, the dual damascene method has been used in fabricating highly efficient and highly stable metallic interconnects for VLSI circuits having a line width smaller than 0.25 .mu.m.
FIGS. 2A through 2D are cross-sectional views showing the progression of manufacturing steps in fabricating metallic interconnects using a conventional dual damascene process. First, as shown in FIG. 2A, a semiconductor substrate 200 is provided. Then, an inter-metal dielectric layer 201, preferably an oxide layer, is deposited over the substrate 200. Thereafter, a first photolithographic and etching operation is carried out to from an opening 202 in the inter-metal dielectric layer 201.
Next, as shown in FIG. 2B, a second photolithographic and etching operation is carried out to form a second opening 203 that exposes the semiconductor substrate 200 at the bottom of the first opening 202. The second opening 203 has a width smaller than the width of the first opening 202.
Next, as shown in FIG. 2C, metallic material is deposited into the first opening 202 and the second openings 203 to form a metallic layer 204. Here, the width of the first opening 202 must be wider so that operation will not be limited by the resolution of photolithography.
Thereafter, as shown in FIG. 2D, the metallic layer 204 is etched back or polished using a chemical-mechanical polishing (CMP) method until the upper surface of the inter-metal dielectric layer 201 is exposed. Ultimately, the metallic layer 204 and the inter-metal dielectric layer are at the same height level.
In summary, as line width of semiconductor devices continues to be reduced, conventional methods of fabricating interconnects have at least the following defects:
1. The conventional method of depositing metal into a via hole often leads to the generation of voids due to poor step coverage of the metal. Furthermore, a glue/barrier layer must be formed prior to the formation of the tungsten plug so that adhesion between subsequently deposited metallic layer and other materials can be increased. PA1 2. Misalignment often occurs when via holes are patterned over the conductive lines. PA1 3. The convention method of fabrication involves a large number of steps. Therefore, production time is longer and production cost is higher.
In light of the foregoing, there is a need to provide abetter method of fabricating interconnects with dual damascene process.